1. Field of the Invention
The present invention relates to fabrication of electronic devices and, in particular, relates to etching layers in the fabrication of integrated circuits.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of data. Conventional semiconductor electronic storage devices typically incorporate capacitor and transistor type structures, which are referred to as Dynamic Random Access Memory (DRAM) that temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection. Many of these capacitor structures are fabricated with layers of material including semiconductor, dielectric, and metal.
One highly effective capacitor structure is the double-sided container capacitor. Such a device is described in U.S. Pat. No. 6,451,661 to DeBoer et al. Double-sided container capacitors typically have a cup-shaped lower electrode. A capacitor dielectric is applied over the lower electrode both internally and externally to the cup-shaped lower electrode. The upper electrode is then deposited over the capacitor dielectric. By employing this folding shape, the capacitor uses a relatively small amount of real estate on the integrated circuit but provides a suitably high capacitance.
Some capacitor structures have lower electrodes that are fabricated by first forming sacrificial spacers within a recess in a substrate, and then forming the lower electrode within the recess and between the sacrificial layer on the sidewalls of the recess. Such a method is described in co-owned U.S. patent application Ser. No. 10/714,115, which was filed on Nov. 13, 2003. The selection of the materials used for the lower electrode material is often dictated by the availability of an etching process with a suitably high selectivity ratio between the two materials. The selectivity ratio is defined as the difference of the removal rate between two materials during an etching process. Typically, an etching process is considered selective if the selectivity ratio is greater than 10 to 1, but for many applications, that selectivity ratio is not sufficient. The sacrificial spacer must be etched away without significantly damaging the surrounding layers, especially the lower electrode. In addition to DRAM, other memory arrays, such as ferroelectric and magnetic RAM, require separation of cells from one another.
There are two major methods of etching integrated circuits (ICs). First, dry etching involves the use of plasma processes to remove films from the substrate. While this method is usually very accurate, it is expensive and can cause damage to underlying layers, as it typically has poor selectivity due to a significant physical component to the etch. Wet etching involves using chemicals usually in an aqueous solution with etching chemicals such as hydrofluoric acid, nitric acid, and acetic acid. While wet etching is isotropic, meaning that it etches in all directions equally, this process is more cost-effective, allows batch processing of wafers, and is typically more selective than dry etching.
Hydrofluoric (HF) acid chemistry solutions are used to etch many films, primarily silicon oxide. Although they can be slower, dilute HF chemistries are often used to control the etching process for other films. Generally, a HF solution is considered to be dilute if the concentration is less than about 100:1. For example, aluminum nitride (AlN) is etched by a solution of 500 parts water to 1 part HF at a rate of about 60 Å per minute. Hafnium nitride (HfN) is etched by the same solution at a rate of about 90 Å per minute. Standard borophosphosilicate glass (BPSG) etches at about 30 Å per minute in this solution. Thus, for example, when using the above solution, the rate of selectivity between HfN and BPSG would be about 3:1.
Many etchants are not sufficiently selective for use in forming DRAM capacitors, or they only allow for a limited selection of materials to be used as the sacrificial spacer and lower electrode. Different etchants must be used for capacitor structures with different electrodes and spacers. This adds costs and inefficiencies to the fabrication process. Improved selectivity of etch is similarly desirable in a variety of other contexts for semiconductor fabrication. Hence, there currently exists a need to reduce manufacturing costs associated with fabricating capacitor structures by simplifying inefficient procedures. To this end, there also exists a need to increase fabrication efficiency by improving the processing techniques associated with fabricating capacitor structures.